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MC74LVX257 Quad 2-Channel Multiplexer with 3-State Outputs
The MC74LVX257 is an advanced high speed CMOS quad 2-channel multiplexer fabricated with silicon gate CMOS technology. It consists of four 2-input digital multiplexers with common select (S) and enable (OE) inputs. When (OE) is held High, selection of data is inhibited and all the outputs go Low. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
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* * * * * * * * * * * *
High Speed: tPD = 4.5 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA Chip Complexity: FETs = 100; Equivalent Gates = 25 ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available*
SOIC-16 D SUFFIX CASE 751B 1
LVX257 AWLYWW
16 TSSOP-16 DT SUFFIX CASE 948F 1 LVX 257 ALYW
16 SOEIAJ-16 M SUFFIX CASE 966 1 LVX257 ALYW
A WL or L Y WW or W
= = = =
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
March, 2005 - Rev. 3
Publication Order Number: MC74LVX257/D
MC74LVX257
I0a S A0 B0 Y0 A1 B1 Y1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OE A3 B3 Y3 A2 I0d B2 Y2 OE 15 I1d I1a I0b I1b I0c I1c 2 3 5 6 14 13 11 10 4 Za
7
Zb
12
Zc
9
Zd
Figure 1. Pin Assignment
S 1
Figure 2. Expanded Logic Diagram
OE S A0 B0 A1 B1 A2 B2 A3 B3 15 1 2 3 5 6 11 10 14 13 EN G1 1 1 MUX 4 7 9 12 Y0 Y1 OE Y2 Y3
FUNCTION TABLE
Inputs S Outputs Y0 - Y3
Figure 3. IEC Logic Symbol
H X Z L L A0 -A3 L H B0 -B3 A0 - A3, B0 - B3 = the levels of the respective Data-Word Inputs.
ORDERING INFORMATION
Device MC74LVX257D MC74LVX257DG MC74LVX257DR2 MC74LVX257DR2G MC74LVX257DT MC74LVX257DTR2 MC74LVX257M MC74LVX257MEL MC74LVX257MELG Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74LVX257
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SOIC Package TSSOP SOIC Package TSSOP Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHU
P
Latchup Performance Thermal Resistance, Junction-to-Ambient
mA C/W
qJA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V Min 2.0 0 0 -40 0 Max 3.6 5.5 VCC 85 100 Unit V V V C ns/V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
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MC74LVX257
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Maximum 3-State Leakage Current Input Leakage Current Maximum Quiescent Supply Current (per package) IOH = -50 mA IOH = -50 mA IOH = -4 mA IOL = 50 mA IOL = 50 mA IOL = 4 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5 V or GND VIN = VCC or GND Condition (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 0 to 3.6 3.6 1.0 1.0 1.9 2.9 2.58 2.0 3.0 0.0 0.0 0.1 0.1 0.36 0.1 0.1 2.0 Min 0.75 VCC 0.7 VCC 0.7 VCC 0.25 VCC 0.3 VCC 0.3 VCC 1.9 2.9 2.48 0.1 0.1 0.44 1.0 1.0 40 TA = 25C Typ Max -40C TA 85C Min 0.75 VCC 0.7 VCC 0.7 VCC 0.25 VCC 0.3 VCC 0.3 VCC Max Unit V
VIL
V
VOH
V
VOL
V
IOZ IIN ICC
mA mA mA
II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I III I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I III I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III II I I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I III I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I III I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III II I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I
TA = 25C Typ 6.5 9.5 4.5 7.5 -40C TA 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Symbol tPLH, tPHL Parameter Test Conditions Min Max Unit ns Maximum Propagation Delay, A or B to Y VCC = 2.7 V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 10.0 14.0 15.0 18.5 10.0 13.5 17.0 20.0 12.0 15.5 16.5 18.0 VCC = 3.3 V 0.3 V VCC = 2.7 V 8.0 12.0 tPLH, tPHL Maximum Propagation Delay, S to Y 8.0 10.5 6.0 8.5 12.0 15.5 10.0 13.5 ns VCC = 3.3 V 0.3 V tPZL, tPZH Maximum Output Enable, Time, OE to Y VCC = 2.7 V RL = 1 kW CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF 7.5 10.5 5.5 8.5 11.5 15.0 9.5 13.0 ns VCC = 3.3 V 0.3 V RL = 1 kW VCC = 2.7 RL = 1 kW 11.5 15.0 tPLZ, tPHZ Maximum Output Disable, Time, OE to Y 13.0 12 4 17.0 17.0 10 18.0 18.0 10 ns VCC = 3.3 V 0.3 V RL = 1 kW CL = 50pF CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 3.3 V 20 CPD Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
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MC74LVX257
NOISE CHARACTERISTICS Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 3.3 V
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.3 -0.3 Max 0.5 -0.5 2.0 0.8 Unit V V V V
OE VCC A, B or S 50% tPLH Y 50% VCC Y tPHL GND Y
50% tPZL 50% VCC tPZH 50% VCC tPHZ tPLZ
VCC GND HIGH IMPEDANCE VOL + 0.3V VOH - 0.3V HIGH IMPEDANCE
Figure 4. Switching Waveform
Figure 5. Switching Waveform
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST
TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
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MC74LVX257
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE N-N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC -W- M 0_ 8_ 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
SECTION
MC74LVX257
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74LVX257
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74LVX257/D

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